Forum Post: RE: Trying to implement jesd204b protocol between ADRV9009 and ZC706 using TCL files provided by EngineerZone. Hi, Thank you for letting us know, we were able to reproduce this on our end. Could you confirm whether or not this is happening with the main HDL and no-OS branch as well? Also, could you try all the combinations for a loopback between Tx and Rx? To eliminate the possibility of a hardware issue. Best regards, Iulia
https://ez.analog.com/fpga/f/q....-a/578477/trying-to-