Forum Post: RE: Versal AD9082 FMCA-EBZ M4 L8 JESD204C design - cont. (SYSREF alignment error) Hi iulia and bluncan , I checked the SYSREF pin as you suggested, the constraints are: set_property -dict {PACKAGE_PIN U27 IOSTANDARD LVDS15} [get_ports sysref2_n] set_property -dict {PACKAGE_PIN V27 IOSTANDARD LVDS15} [get_ports sysref2_p] which I believe it's correct for VPK120. Problem is, the issue persists even when I set subclass = . Can this provide some new insights? Could you kindly upload the full VPK180 M4 L8 JESD204C design to your GitHub repository? Or could you at least upload the full device tree files set? Thank you for your support! EW1
https://ez.analog.com/fpga/f/q....-a/594484/versal-ad9

Forum Post: RE: Sample Rates Hi, We would have to create a setup for this to validate in hardware, but we can do this only next week. Please remind us if you receive no response by mid-next week. Best regards, Iulia
https://ez.analog.com/fpga/f/q....-a/595553/sample-rat

Forum Post: RE: Sample Rates Thank you, that would be greatly appreciated. In the meantime are you able to confirm the frequency of the vcxo that we would need to replace the current part on the ADRV9009?
https://ez.analog.com/fpga/f/q....-a/595553/sample-rat

Forum Post: RE: AXI_9361 cycle delay Hi, To me it seems that there are 8 or more, depending if the iq correction or dc filters are active. And yes those are needed. ez.analog.com/.../7220.schematic.pdf
https://ez.analog.com/fpga/f/q....-a/595528/axi_9361-c

Forum Post: RE: Can AXI-Lite registers be created and accessed via pyadi-iio (W/R)? pyadi is just a layer ontop of libiio, so if the IIO driver exposes register control then so can pyadi. [quote userid="129361" url="~/fpga/f/q-a/595534/can-axi-lite-registers-be-created-and-accessed-via-pyadi-iio-w-r"]mwipcore0[/quote] This driver is really just a generic driver that just exposes registers for IP that is AXI compliant as those generated by HDL-Coder. Each instance of mwipcore0 would be a separate IP or memory region. So you don't at a new driver for every register. In Simulink+HDL-Coder these would just be ports that get assigned an offset during codegen. -Travis
https://ez.analog.com/fpga/f/q....-a/595534/can-axi-li