Forum Post: RE: Vivado Partial Routing to BUFR To deal with the 1R1T mode. In the devicetree, have you changed the compatible to ad9364 or use the fmcomms4 devicetrees? this will automatically configure everything for 1R1T. linux/arch/arm/boot/dts/adi-fmcomms4.dtsi at 2018_R2 · analogdevicesinc/linux linux/arch/arm/boot/dts/zynq-zc706-adv7511-ad9364-fmcomms4.dts at 2018_R2 · analogdevicesinc/linux The data transfer is managed by valid and enable signals, so, I would not worry that the clock is 2x faster. You are working on an older version of the HDL, to my knowledge the behaviour should be the same, not 100% sure though. Also if your only plan to use 1R1T mode you can spare some logic, by setting this param at build time. hdl/library/axi_ad9361/axi_ad9361.v at hdl_2018_r2 · analogdevicesinc/hdl Andrei
https://ez.analog.com/fpga/f/q....-a/593213/vivado-par

Forum Post: RE: Unable to effectively access the address space of adi dmac 我发现只有地址的最后一位为0的寄存器才可以正常访问。 I found that only registers with the last bit of the address being 0 can be accessed normally. root@ubuntu-arm64-zynqmp:/home/xilinx# busybox devmem 0xa0008000 32 0x00040461 root@ubuntu-arm64-zynqmp:/home/xilinx# busybox devmem 0xa0008004 32 0x00000000 root@ubuntu-arm64-zynqmp:/home/xilinx# busybox devmem 0xa0008008 32 0x00000000 root@ubuntu-arm64-zynqmp:/home/xilinx# busybox devmem 0xa000800c 32 0x00000000 root@ubuntu-arm64-zynqmp:/home/xilinx# busybox devmem 0xa0008010 32 0x00082404 root@ubuntu-arm64-zynqmp:/home/xilinx# busybox devmem 0xa0008014 32 0x00000000 root@ubuntu-arm64-zynqmp:/home/xilinx# busybox devmem 0xa0008080 32 0x00000003 root@ubuntu-arm64-zynqmp:/home/xilinx# busybox devmem 0xa0008400 32 0x00000000 root@ubuntu-arm64-zynqmp:/home/xilinx# busybox devmem 0xa0008410 32 0x40010000 root@ubuntu-arm64-zynqmp:/home/xilinx# busybox devmem 0xa0008000 128 devmem: bad width root@ubuntu-arm64-zynqmp:/home/xilinx# busybox devmem 0xa0008000 64 0x0000000000040461 root@ubuntu-arm64-zynqmp:/home/xilinx# busybox devmem 0xa0008410 64 0x0000000040010000
https://ez.analog.com/fpga/f/q....-a/593361/unable-to-

Forum Post: RE: HW/SW Co-Design QPSK Transmit and Receive Using AD9361/AD9364 - Vitis Implementation Thank you for your response
https://ez.analog.com/fpga/f/q....-a/593195/hw-sw-co-d

Forum Post: Unexpected Received Data from AD9361 on ZedBoard + FMCOMMS3 I am working with the AD9361 reference project on a ZedBoard + FMCOMMS3 setup. I am transmitting a constant pattern (0x55555555) and expecting to receive the same pattern (or a variation due to analog effects). However, the received data is completely different from the expected transmission.Why can't I receive what I sent? Steps to Reproduce: I generate a 1024-sample array filled with 0x55555555 and load it into the TX DMA buffer. I configure the DAC to use this custom data and enable transmission. I capture 1024 received samples and print them. ---- Code Snippet: ----- ----- 1-Transmit Data Setup ------ uint32_t constant_tx_data[1024]; for (int i = 0; i tx_dac, -1, AXI_DAC_DATA_SEL_DMA); axi_dac_load_custom_data(ad9361_phy->tx_dac, constant_tx_data, NO_OS_ARRAY_SIZE(constant_tx_data), (uintptr_t)dac_buffer); ------ 2- Received Data Printout -------- for (int i = 0; i < 1024; i++) { printf("0x%08X
", adc_buffer[i]); } ------ 3-OUTPUT -------- 0x00002CD4 0x00002CAF 0x0000FA6D 0x0000FA04 0x0000D2EA 0x0000D2DA 0x0000FA6E 0x0000FA04 ...
https://ez.analog.com/fpga/f/q....-a/593575/unexpected

Forum Post: RE: ADRV9009 work in bandwidth 450Mhz and sample rate 491.04Msps Hi, Do you have any other questions regarding this issue? Can we close it? Best regards, Andrei
https://ez.analog.com/fpga/f/q....-a/590539/adrv9009-w