Forum Post: RE: Issues while trying to write/read using DMA to/from PS DDR Hi , Here we are implementing the same design with Multiple AD9361 on our board, which is not a ZCU102. We are having a user clock with a frequency of 40 MHz which is a single-ended clock. Could you please confirm if this clock frequency can be used as the ref_clk?
https://ez.analog.com/fpga/f/q....-a/580453/issues-whi