Forum Post: RE: Issues while trying to write/read using DMA to/from PS DDR > I personally would prefer to drive the AD9361 with a differential clock, however. Our custom board is having only this 40MHz as the external clock . > Does your ref_clk do through a clock buffer like ADCLK846 and then the AD9361 is driven by a differential clock? We are generating Single ended 40 MHz from a clock buffer chip which is driven by a TCXO.
https://ez.analog.com/fpga/f/q....-a/580453/issues-whi