Forum Post: Reference design for JESD204B timestamp synchronization Hi, I'd like to use JESD204B subclass0 to do timestamp synchronization for our ad9695 multi-chip system. However, I browsed through your hdl reference designs and I can't find any of them adopt the timestamp method. The similar one I found is the ad9208_dual_ebz , which uses subclass1 to do synchornization by controlling deterministic latency. I believe to use timestamp method, we need to establish ONE jesd link in the RX side and receive all the data from all different TX links. This assumption is based on my previous post . But I'm not sure if it's possible to use the same PHY, LINK and TPL layer to receive data from multiple channels. Can someone help with this? Thanks.
https://ez.analog.com/fpga/f/q....-a/582320/reference-