Forum Post: RE: Vivado Partial Routing to BUFR To deal with the 1R1T mode. In the devicetree, have you changed the compatible to ad9364 or use the fmcomms4 devicetrees? this will automatically configure everything for 1R1T. linux/arch/arm/boot/dts/adi-fmcomms4.dtsi at 2018_R2 · analogdevicesinc/linux linux/arch/arm/boot/dts/zynq-zc706-adv7511-ad9364-fmcomms4.dts at 2018_R2 · analogdevicesinc/linux The data transfer is managed by valid and enable signals, so, I would not worry that the clock is 2x faster. You are working on an older version of the HDL, to my knowledge the behaviour should be the same, not 100% sure though. Also if your only plan to use 1R1T mode you can spare some logic, by setting this param at build time. hdl/library/axi_ad9361/axi_ad9361.v at hdl_2018_r2 · analogdevicesinc/hdl Andrei
https://ez.analog.com/fpga/f/q....-a/593213/vivado-par