Forum Post: no CW signal is observed by DMAC/noOS driver on AD9081_FMCA_EBZ/VCK190 Hi all, We use the following the develop the AD9081_FMCA_EBZ on VCK190. Since the IIO via UART is not working on VCK190, we using the DMAC to transfer the ADC data and print it. However, no CW signal is observed on 8 DAC channel when changing the power and frequency. reference project: https://github.com/analogdevic....esinc/hdl/tree/hdl_2 reference noOS driver: https://github.com/analogdevic....esinc/no-OS/tree/ver modified the configuration app_config.h as the following #define AD9081_RX_MAIN_DECIMATION {1, 1, 1, 1} #define AD9081_RX_CHAN_DECIMATION {1, 1, 0, 0, 1, 1, 0, 0} #define AD9081_RX_MAIN_ENABLE {1, 1, 1, 1} #define AD9081_RX_CHAN_ENABLE {1, 1, 0, 0, 1, 1, 0, 0} #define AD9081_RX_MAIN_NCO_SHIFT {1000000000, 1000000000, 1000000000, 1000000000} #define AD9081_RX_CHAN_NCO_SHIFT {0, 0, 0, 0, 0, 0, 0, 0} modified the main app.c as the following axi_dmac_init(&tx_dmac, &tx_dmac_init); /* Initialize the DAMC core */ status = axi_dmac_init(&rx_dmac, &rx_dmac_init); if (status) { printf("axi_dmac_init rx init error: %"PRIi32"
", status); return status; } int16_t *adc_buffer; adc_buffer = (int16_t *) malloc(1000*sizeof(int16_t)); int16_t n1; struct axi_dma_transfer read_transfer = { // Number of bytes to write/read .size = 1000, // Transfer done flag .transfer_done = 0, // Signal transfer mode .cyclic = NO, // Address of data source .src_addr = 0, // Address of data destination .dest_addr = (uintptr_t)adc_buffer }; /* Read the data from the ADC DMA. */ axi_dmac_transfer_start(rx_dmac, &read_transfer); /* Wait until transfer finishes */ status = axi_dmac_transfer_wait_completion(rx_dmac, 10; if(status) return status; Results -1, 1242, -29, -1, -1, 4, -29, -1, -2, -1201, 26, 2, -2, -1, 26, 2, 0, -307, -30, 2, 0, 1, -30, 2, 1, -1, -392, 2, 1, -1, -1630, 2, 3, 0, -766, 2, 3, 0, 765, 2, -1, -3, -1, 1, -1, -3, 355, 1, -2, 0, -1348, 3, -2, 0, -1821, 3, 2, -419, -2, 2, 2, -2, -2, 2, 2, 1693, -2, 2, 2, -1, -2, 2, 4, 864, -2, 0, 4, 0, -2, 0, 1, -5, -1, 2, 1, -5, -1, 2, -2, 38, 1, 1, -2, 2, 1, 1, 2, -751, -2, 2, 2, -3, -2, 2, -2, -1171, -1, 5, -2, -1, -1, 5, 0, -1817, -3, 2, 0, -2, -3, 2, 1, 0, 0, -2, 1, 0, 0, -2, 1, 2, 0, 4, 1, 0, 0, 4, 3, 172, 1, 3, 3, -1, 1, 3, 0, -578, 1, 4, 0, -1, 1, 4, -1, 1240, 0, 1, -1, 0, 0, 1, 1, 512, -2, 0, 1, 0, -2, 0, -1, -4, 0, 1, -1, -1, 0, 1, 0, -43, 1, 2, 0, 2, 1, 2, 1, 1989, 2, 0, 1, -3, 2, 0, 3, -700, -1, 3, 3, 2, -1, 3, 0, 465, 1, 0, 0, 1, 1, 0, -3, -3, 2, 1, -3, -3, 2, 1, -4, -265, 2, 0, -4, 1, 2, 0, 4, -731, -3, 4, 4, 1, -3, 4, 2, 477, 0, -2, 2, -3, 0, -2, 1, -1446, 3, 1, 1, -4, 3, 1, -1, 1, -3, 1, -1, 1, -3, 1, 0, -1568, 2, 4, 0, -1, 2, 4, 0, -1105, -1, 3, 0, -1, -1, 3, 2, -160, 1, -1, 2, 0, 1, -1, 2, -140, 2, 0, 2, -1, 2, 0, 0, -2047, 0, 5, 0, 1, 0, 5, 1, 17, 1, 3, 1, 0, 1, 3, 1, 354, 2, -2, 1, 0, 2, -2, 0, -1070, 1, -2, 0, -3, 1, -2, 0, 1927, 1, 1, 0, 0, 1, 1, 2, -1437, 0, 1, 2, 3, 0, 1, 0, -33, -1, 3, 0, -2, -1, 3, -1, -1159, -2, 0, -1, 0, -2, 0, -1, 1822, 1, 0, -1, 1, 1, 0, 4, 1293, 2, 1, 4, 1, 2, 1, -1, 37, -1, 1, -1, -1, -1, 1, 2, -14, -2, 3, 2, -2, -2, 3, 0, -1211, -2, 1, 0, 0, -2, 1, 1, -1393, 0, 2, 1, -1, 0, 2, 0, -200, -1, 3, 0, 1, -1, 3, -2, 1317, -3, 0, -2, 0, -3, 0, 2, 762, 2, -1, 2, -1, 2, -1, -1, -1424, -1, 3, -1, 2, -1, 3, 0, 319, 0, 2, 0, 0, 0, 2, 0, -59, -2, -2, 0, 1, -2, -2, 1, -491, -3, 4, 1, 0, -3, 4, 2, -49, 0, 0, 2, -1, 0, 0, 1, 1349, 0, 0, 1, 1, 0, 0, 1, -17, 2, 1, 1, 2, 2, 1, 0, -2, -2, 4, 0, 2, -2, 4, -1, 752, -1, -1, -1, 0, -1, -1, 4, 1614, 0, 0, 4, 1, 0, 0, Is there anything missing ? Sincerely H. A.
https://ez.analog.com/fpga/f/q....-a/594928/no-cw-sign