Forum Post: RE: Can AXI-Lite registers be created and accessed via pyadi-iio (W/R)? pyadi is just a layer ontop of libiio, so if the IIO driver exposes register control then so can pyadi. [quote userid="129361" url="~/fpga/f/q-a/595534/can-axi-lite-registers-be-created-and-accessed-via-pyadi-iio-w-r"]mwipcore0[/quote] This driver is really just a generic driver that just exposes registers for IP that is AXI compliant as those generated by HDL-Coder. Each instance of mwipcore0 would be a separate IP or memory region. So you don't at a new driver for every register. In Simulink+HDL-Coder these would just be ports that get assigned an offset during codegen. -Travis
https://ez.analog.com/fpga/f/q....-a/595534/can-axi-li