Forum Post: RE: Versal AD9082 FMCA-EBZ M4 L8 JESD204C design - cont. (SYSREF alignment error) Hi, When you set to subclass 0 in dts , it should say that the sysref is disabled, so that's pretty strange. Unfortunately I cannot upload boot files, but you can build the project with your configuration by changing these build parameters: https://github.com/analogdevic....esinc/hdl/tree/main/ and also the timing_constr.xdc to match your configuration, and dts as Bogdan said here: RE: Versal AD9082 FMCA-EBZ M4 L8 JESD204C design Best regards, Iulia
https://ez.analog.com/fpga/f/q....-a/594484/versal-ad9