Forum Post: RE: Simulink HDL Support for CN0585/CN0584 Hardware-in-the-Loop Application Hello Ezenia , The valid_in port is a signal generated by the LTC2387 IP. This signal is high for only one clock cycle when the data captured by the ADC is valid. The AD3552R IP uses this signal to latch the data that needs to be sent to the AD3552R DAC. Could you please elaborate a bit on the use case and how you would like to use the CN0585 board, especially the Simulink block? Thanks, Paul
https://ez.analog.com/fpga/f/q....-a/594679/simulink-h