Forum Post: RE: Spike over the Received IQ
HI ParasADT , This sounds like a race condition. Probably at boundary between the ADC clock domain and the Digital i/f domain. Haven't found the register map document, but see if there are registers for PLL control. Fiddle with them. Cheers, heke
https://ez.analog.com/fpga/f/q....-a/597160/spike-over
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