Forum Post: RE: Can AXI-Lite registers be created and accessed via pyadi-iio (W/R)? Yes, I will verify the response. Thanks, Travis!
https://ez.analog.com/fpga/f/q....-a/595534/can-axi-li

Forum Post: RE: Simulink HDL Support for CN0585/CN0584 Hardware-in-the-Loop Application Hi Paul, Thanks for the explanation! I want to make filters within the programmable logic and insert that into a path between adc inputs and dac outputs. I recognize that we can choose internal or external signals, but for this application I am focused on filtering external signals I receive from the adc inputs on the CN0584. After filtering, I will output the signal via the dacs. I feel like this image from the Hardware in the Loop section best illustrates what I'm trying to achieve. For my HDL Hardware Model, I will be implementing digital filters: Nothing with Simulink has actually worked, so I'm also working on my own verilog code to insert within the axi_ad3552r_channel module in the ad3552r core. Best, Ezenia
https://ez.analog.com/fpga/f/q....-a/594679/simulink-h

Forum Post: RE: Can AXI-Lite registers be created and accessed via pyadi-iio (W/R)? Hi Ezenia , Were all your questions answered? Can we close this thread now? Regards, Elena
https://ez.analog.com/fpga/f/q....-a/595534/can-axi-li

Forum Post: RE: Simulink HDL Support for CN0585/CN0584 Hardware-in-the-Loop Application Hello Ezenia , The valid_in port is a signal generated by the LTC2387 IP. This signal is high for only one clock cycle when the data captured by the ADC is valid. The AD3552R IP uses this signal to latch the data that needs to be sent to the AD3552R DAC. Could you please elaborate a bit on the use case and how you would like to use the CN0585 board, especially the Simulink block? Thanks, Paul
https://ez.analog.com/fpga/f/q....-a/594679/simulink-h

Forum Post: RE: How to feed data to Tx in ADRV9009 project. I found the correct way to give data in this post: https://ez.analog.com/sw-inter....face-tools/f/q-a/103 " The channels for TX on the ADRV9009 are from 0 to 3, dac_data_0 being I0, dac_data_1 Q0, dac_data_2 I1 and dac_data_3 Q1. the DAC_DATA buscomes from the DMA. Each of the 32 bit dac_data_x bus has two consecutive samples for the channel so if you want to send IQ data for the RF channel 0, you'll need to provide data on the dac_data_0 and dac_data_1 buses. "
https://ez.analog.com/fpga/f/q....-a/165823/how-to-fee