Forum Post: RE: Versal AD9082 FMCA-EBZ M4 L8 JESD204C design - cont. (SYSREF alignment error) Hi iulia , 1. The timing_constr.xdc file I use (uploaded above) is practically identical to the default file here: https://github.com/analogdevic....esinc/hdl/blob/main/ Do you think this is correct? 2. Reading your reply, I recalled an issue I had during the VPK180-to-VPK120 migration. When I built the VPK180 design, I specified M4 L8 JESD204C. However, in the system_top.v file, the parameters written are: module system_top #( parameter TX_JESD_L = 4, parameter TX_NUM_LINKS = 1, parameter RX_JESD_L = 4, parameter RX_NUM_LINKS = 1, parameter JESD_MODE = "8B10B", parameter GENERATE_LINK_CLK = 1 Apparently, this isn’t a problem, since the parameters are bound to the correct values by the build scripts. However, when building the design for VPK120 using Vivado, I had to explicitly write the correct values, in order to avoid an error: module system_top #( parameter TX_JESD_L = 8, parameter TX_NUM_LINKS = 1, parameter RX_JESD_L = 8, parameter RX_NUM_LINKS = 1, parameter JESD_MODE = "64B66B", parameter GENERATE_LINK_CLK = 1 Does this make sense? Best of regards, EW1
https://ez.analog.com/fpga/f/q....-a/594484/versal-ad9

Forum Post: RE: Reconfigure the adrv9009/zcu102 reference design to use a 100MSPS rate Hi Iulia, Thank you for the update; we appreciate your efforts on our behalf! Best Regards, -Steve Sc
https://ez.analog.com/fpga/f/q....-a/595445/reconfigur

Forum Post: RE: Unable to fix the ORX IQ samples in stitching mode No updates. Issue resolved
https://ez.analog.com/fpga/f/q....-a/582017/unable-to-

Forum Post: RE: 1MHz Sine Tone Generation Hi Pronadeep , do you have any updates?
https://ez.analog.com/fpga/f/q....-a/595128/1mhz-sine-

Forum Post: RE: Reconfigure the adrv9009/zcu102 reference design to use a 100MSPS rate Hi, Yes, it is the right group. These past days a colleague was trying to reproduce the issue, and finally we were able, but we're still investigating. [quote userid="133259" url="~/fpga/f/q-a/595445/reconfigure-the-adrv9009-zcu102-reference-design-to-use-a-100msps-rate/569520"]From Boot Log Section 1, the axi_adxcvr_drv tx has number of lanes 4 and axi_jesd204-tx has number of lanes 2. Is this correct?[/quote] Yes. [quote userid="133259" url="~/fpga/f/q-a/595445/reconfigure-the-adrv9009-zcu102-reference-design-to-use-a-100msps-rate/569520"]Which clock are you talking about raising to 200MHz? [/quote] The refclk, but it didn't seem to help when we tested, so you can dismiss this. Unfortunately, at the moment I do not have more information. Best regards, Iulia
https://ez.analog.com/fpga/f/q....-a/595445/reconfigur