Forum Post: zcu102 adrv9009 IPs not work on zcu11eg Hi， I am doing revise the FPGA reference design from zcu9eg(ZCU102) + adrv9009 to zcu11eg + adrv9009. After I changed the IO , I hoped the app can initialize the hardware. But the error occured at IP axi_adrv9009_rx_clkgen, axi_adrv9009_rx_os_clkgen, axi_adrv9009_tx_clkgen. I traced the app code to find the error at checking if reg_val == AXI_CLKGEN_STATUS, but the read reg_val is zero. I review the memory map and find the memory of the IPs 0x83C00000， 0x83C10000， 0x83C20000，are all zeroes. If I used the orignal zcu9eg(ZCU102) + adrv9009 , the app worked fine and the memory are not all zeroes. I have no idea how to make the IPs work on zcu11eg as well as zcu9eg?
https://ez.analog.com/fpga/f/q....-a/593593/zcu102-adr

Forum Post: RE: zcu102 adrv9009 IPs not work on zcu11eg I used the revised hardware(zcu11eg) , excluding the IPs , only MPSOC and DDR , to implement the ZynqMP DDR test . The result is ok. So PS DDR is fine.
https://ez.analog.com/fpga/f/q....-a/593593/zcu102-adr

Forum Post: RE: Unable to effectively access the address space of adi dmac I've found the reason. In the Vivado project, I connected the s_axi interface of the ADI-AXI-DMA-Controller to M_AXI_HPM0_FPD . The correct connection should be to M_AXI_HPM0_LPD .
https://ez.analog.com/fpga/f/q....-a/593361/unable-to-

Forum Post: RE: FMCOMMS5 on ZCU106 HDL Hi, We did a further check and there are a few pins that don't have a corresponding match on the zcu106. gpio_debug_3_1, gpio_debug_4_1, gpio_ctl_1[3], gpio_status_1[7], gpio_calsw_3_1, gpio_calsw_4_1, gpio_en_agc_1, gpio_resetb_1. This means it will not work out of the box. There are a some probe connectors that you can tap in an control those lines from zcu106 PMODs. But, there is a catch, the PMOD is at 3.3V and the AD9361 needs 1.8V, so there is a need for a level translation between the PMOD and fmcomm5. Also, to fit the board you will be forced to unsolder a SMA connector. And there are not enough PMOD pins. 4 extra are need... Maybe a gpio expander... So, not sure it worth's the effort. Andrei
https://ez.analog.com/fpga/f/q....-a/593007/fmcomms5-o

Forum Post: RE: ADRV9008-1 RF Receiver with the Xilinx Kintex UltraScale FPGA using the JESD204B protocol Hi Rajaseharan , Please take a look at this thread (+) Reference Project for KU115 with ADRV9008-1 - Q&A - FPGA Reference Designs - EngineerZone and tagging danmois for Vitis flow. Best regards, Bianca
https://ez.analog.com/fpga/f/q....-a/593538/adrv9008-1