Forum Post: RE: Unable to fix the ORX IQ samples in stitching mode No updates. Issue resolved
https://ez.analog.com/fpga/f/q....-a/582017/unable-to-

Forum Post: RE: 1MHz Sine Tone Generation Hi Pronadeep , do you have any updates?
https://ez.analog.com/fpga/f/q....-a/595128/1mhz-sine-

Forum Post: RE: Reconfigure the adrv9009/zcu102 reference design to use a 100MSPS rate Hi, Yes, it is the right group. These past days a colleague was trying to reproduce the issue, and finally we were able, but we're still investigating. [quote userid="133259" url="~/fpga/f/q-a/595445/reconfigure-the-adrv9009-zcu102-reference-design-to-use-a-100msps-rate/569520"]From Boot Log Section 1, the axi_adxcvr_drv tx has number of lanes 4 and axi_jesd204-tx has number of lanes 2. Is this correct?[/quote] Yes. [quote userid="133259" url="~/fpga/f/q-a/595445/reconfigure-the-adrv9009-zcu102-reference-design-to-use-a-100msps-rate/569520"]Which clock are you talking about raising to 200MHz? [/quote] The refclk, but it didn't seem to help when we tested, so you can dismiss this. Unfortunately, at the moment I do not have more information. Best regards, Iulia
https://ez.analog.com/fpga/f/q....-a/595445/reconfigur

Forum Post: RE: 1MHz Sine Tone Generation Hi I am checking with the design team. I will get back to you with more details. Thanks & Regards, Pronadeep
https://ez.analog.com/fpga/f/q....-a/595128/1mhz-sine-

Forum Post: RE: Versal AD9082 FMCA-EBZ M4 L8 JESD204C design - cont. (SYSREF alignment error) Hi, When you set to subclass 0 in dts , it should say that the sysref is disabled, so that's pretty strange. Unfortunately I cannot upload boot files, but you can build the project with your configuration by changing these build parameters: https://github.com/analogdevic....esinc/hdl/tree/main/ and also the timing_constr.xdc to match your configuration, and dts as Bogdan said here: RE: Versal AD9082 FMCA-EBZ M4 L8 JESD204C design Best regards, Iulia
https://ez.analog.com/fpga/f/q....-a/594484/versal-ad9