Forum Post: RE: VCK190 + AD9082 with S=1 Hi, you are right again.. I have placed the 'hdl' repo in the root folder (i.e. C, AND I changed the name of 'C:/hdl/projects/ad9082_fmca_ebz' to 'C:/hdl/projects/ 8 2 '. Now the custom design is generated successfully. Thank you very much for your kind help! EW1
https://ez.analog.com/fpga/f/q....-a/582667/vck190-ad9

Forum Post: RE: VCK190 + AD9082 with S=1 It's not necessary to be that short. For example, my path until the "hdl" folder is 30 characters long and it's perfectly fine, then to add the /projects/ad9082_fmca_ebz/zcu102, I have no issues building the projects. (if I'm not mistaken, I think the limit is 200 or 220, you should check on their forum) But I'm glad you were able to build the project. I will close now this thread. Best regards, Iulia
https://ez.analog.com/fpga/f/q....-a/582667/vck190-ad9

Forum Post: RE: How to use AD9361 to comlete OFDM data transmit? Does FPGA need a Hardware or software microprocessor?
https://ez.analog.com/fpga/f/q....-a/582734/how-to-use

Forum Post: RE: VCK190 + AD9082 with S=1 Could it be from a long path to the folder? https://support.xilinx.com/s/q....uestion/0D54U00005cV Maybe try to move the repo at a higher-up folder in the hierarchy. You didn't have issues with the default design probably because the path didn't exceed the limit set by Vivado. For yours, It creates a folder name like RXS1_TXS1_TXNP16_RXNP16 and it adds quite a bit of characters.
https://ez.analog.com/fpga/f/q....-a/582667/vck190-ad9

Forum Post: RE: VCK190 + AD9082 with S=1 Yes they do. I'm able to generate the default design with no problems. EW1
https://ez.analog.com/fpga/f/q....-a/582667/vck190-ad9