Forum Post: RE: Spike over the Received IQ If you would have a Spectrum analyser this would be easier. Just look at the Tx side, for now. You are looking a the DC. Or what is that scale for frequency domain. What is the frequency of the DDS sine you are sending? I would look on an interval twice the sampling window or more. Andrei
https://ez.analog.com/fpga/f/q....-a/597160/spike-over

Forum Post: RE: Support for Kria K24 SOM There is another parameter form the validation list you updated, that needs a corresponding value. This might help (+) ADRV9002 to Kria K26? - Q&A - FPGA Reference Designs - EngineerZone Andrei
https://ez.analog.com/fpga/f/q....-a/598598/support-fo

Forum Post: RE: Spike over the Received IQ Hi Stanca , I have computed the FFT of the incoming 10 kHz IQ signal, and the results are provided below. Regards, PADT
https://ez.analog.com/fpga/f/q....-a/597160/spike-over

Forum Post: RE: ADRV9002 LSSI interfaces on Arria 10 Hi, I'm planning to design ADRV9002 with Arria 10 GX FPGA, if i want to make LSSI 2 lane work at 40MHZ BW what i should take care. Can you suggest. -- Regards Vivek V
https://ez.analog.com/fpga/f/q....-a/540664/adrv9002-l

Forum Post: RE: ADRV9002 LSSI interfaces on Arria 10 Hello, Since this is a closed and old thread, please open a new one, providing all the details you find relevant for your use case. Kind regards, Stanca
https://ez.analog.com/fpga/f/q....-a/540664/adrv9002-l