Forum Post: RE: zc706, u-boot_zynq_zc706.elf Hi simbasoft , Indeed, the u-boot defconfig used to build the u-boot.elf for all zc706 projects is the "zynq_zc706_defconfig" from https://github.com/analogdevicesinc/u-boot-xlnx , default branch. This is a fork from Xilinx u-boot repo (an older version of it) with ADI changes on top. Sorry for delay. Stefan
https://ez.analog.com/fpga/f/q....-a/582080/zc706-u-bo

Forum Post: ADRV9009-ZU11EG/ADRV2CRR-FMC RF synchronization with 10 MHz/ 1 PPS external reference clock Hello, I need to synchronize the ADRV9009 RX sampling clock with an external provided 10-MHz reference clock (PPS aligned reference clock source) on a ADRV9009-ZU11EG RF/ADRV2CRR-FMC based system. Using the approach described in https://ez.analog.com/fpga/f/q....-a/539645/using-pps- I get the AD9545 reporting a successfully lock on the 10-MHz reference clock provided on J4 of the ADRV2CRR-FMC carrier board: >cat /sys/kernel/debug/clk/Ref-A-Div/Ref-A-Div Ref-A-Div: Reference: Valid >cat /sys/kernel/debug/clk/PLL0/PLL0 PLL0: PLL status: Locked Freerun Mode: Off Holdover Mode: Off PLL Profile: On Profile Number: 1 Temperature: 54 C The AD9545 output OUT0_A_P/N is connected to CLKIN0/RFSYNCIN/CLKIN0/RFSYNCIN_N of the HMC7044 on the carrier board. Reading https://wiki.analog.com/resour....ces/eval/user-guides it is clear that the HMC7044 on the carrier board is responsible for the alignment of the reference clock with an external reference. On https://wiki.analog.com/_media..../resources/eval/user on the path between the AD9545 and the HMC7044, there is the mention of jumpers R257 and R260 (strange since jumpers are usually indicated using the letter J) and the wire between the two ICs is showed as a dotted wire (suggesting that this is somehow optional)... On the schematic of ADRV2CRR-FMC R257 and R260 (which are resistors and not jumpers) are on the Expansion header ... I therefore guess they have nothing to do with the clocking system. On my system I implemented a free running programmable counter clocked by the ADRV9009 RX sampling clock. This programmable counter has a phase alignment mechanism which allows me to re-phase the counter in order to align to the 1-PPS signal used to synchronize the 10 MHz reference clock source. The overflow of such counter generates a pulse winch I connected to an external accessible SMA. By programming the counter with an overflow value of 245.76e6 (default ADRV9009 RX sampling frequency), I expect the generated pulse (measurable on the previously mentioned SMA) to have a stable phase relationship with the reference 10-MHz (which is phase aligned to a PPS signal). Unfortunately this is not the case. The counter generated pulse is aligning to the PPS signal when I request to do it, but it then "rapidly" drift's away from the PPS rising edge (the drift direction deepens on the system temperature)... This suggests me that the ADRV9009 RX sampling clock is not aligned or phase locked on the 10 MHz reference clock provided on J4. Is there anything I need to do, other than modifying the DT in order to have the AD9545 locking on the J4 10 MHz, in order to align/lock the ADRV9009 RX sampling clock to the 10-MHz signal on J4 (ex. adding some stuff to the hmc7044_car DT node)? What about the jumpers R257/260 mentioned in picture adrv9009_rfsom_clocking_tree.png ? Many thanks for any input... Joel
https://ez.analog.com/fpga/f/q....-a/583375/adrv9009-z

Forum Post: RE: Building an HDL Project Hi, In the wiki page it says [output-archive] because the output archive is an optional parameter. You wrote it 1:1 but there is no file called "output-archive", it's named differently and the script doesn't know how to interpret the square brackets. We used that as an umbrella for the archive, I hope you understand what I mean. To run a script, use "./" before the name of the script. In the wiki page, we also said that the "u-boot.elf" file should be put as a parameter, but you have to adapt the name depending on your case. Give it a little bit of thought. Between your files, there's no "u-boot.elf" file, but " u-boot_xilinx_zynqmp_zcu102_revA.elf". So this you should put as parameter in your command, as ZCU102 is your carrier thus the name "u-boot_xilinx_zynqmp_zcu102_revA.elf". Again, "u-boot.elf" is a umbrella term for all the u-boot files. Best regards, Iulia
https://ez.analog.com/fpga/f/q....-a/582601/building-a

Forum Post: RE: Path from FPGA to ASIC It depends on the design. Which one are you interested in? You might have issue if the HDL design uses DSPs. Andrei
https://ez.analog.com/fpga/f/q....-a/583352/path-from-

Forum Post: Path from FPGA to ASIC Hello, If I get an FPGA design completed, in the future can I turn it into an asic to reduce cost? Thanks, Harry
https://ez.analog.com/fpga/f/q....-a/583352/path-from-